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ISL78100
Data Sheet December 17, 2007 FN6626.0
High Power LED Driver
The ISL78100 is a high-power LED backlight driver with an integrated 36V FET designed to drive up to 8 high-power LEDs in series. The PWM converter runs from an internally generated 1MHz clock. With efficiencies over 90%, the regulator provides tight control of LED current and may be configured in either boost or buck topologies, allowing from 3 to 8 series diodes to be driven from wide input voltages. LED light level may be controlled either by: 1. LED DC bias current set via the LEVEL pin, or 2. External low frequency PWM control via the ENABLE/PWM pin. In both control modes, optional over-temperature thermal protection of the LED reduces the LED DC bias current above an adjustable set temperature, protecting the LED from thermal damage. An optional fault monitor drives an external FET between the input supply and inductor, providing short circuit current protection for the LED and inductor as well as load dump protection for automotive applications. For low cost applications the pass transistor may be omitted and the fault pin bypassed. The ISL78100 is packaged in a 20 Ld 4mmx4mm QFN package and is specified for operation over the -40C to +105C temperature range.
Features
* Drives 3 to 8 high-power LEDs in series, up to 32V * 2.7V to 16V input voltage range * Boost or Buck configurable switch * 3A integrated FET * Automotive load dump protection * Light output temperature compensation * LED over-temperature protection * LED disconnect * PWM/analog light level control * Small, 20 Ld 4mmx4mm QFN package * TS-16949 and AEC-Q100 Compliant * Pb-free (RoHS compliant)
Applications
* Automotive display backlighting * Automotive LED lighting
Pinout
ISL78100 (20 LD 4X4 QFN) TOP VIEW
19 FAULT 16 VBAT 15 ENL 14 MODE THERMAL PAD 13 EN/PWM 12 SWS1 11 SWS2 BUCK/BOOSTN 6 LEVEL 7 TMAX 10 TEMP 8 FB 9 18 GND
Ordering Information
PART NUMBER (Note) ISL78100ARZ ISL78100ARZ-TK* ISL78100ARZ-T* PART MARKING 781 00ARZ 781 00ARZ 781 00ARZ PACKAGE (Pb-free) 20 Ld 4x4 QFN 20 Ld 4x4 QFN Tape and Reel 20 Ld 4x4 QFN Tape and Reel PKG. DWG. # L20.4x4C L20.4x4C L20.4x4C
SWD1 4 SWD2 5 VDC 1 VHI 2 OVP 3
20 VIN
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
17 NC
ISL78100
Absolute Maximum Ratings (TA = +25C)
Maximum pin voltage, all pins except below 6.5V VIN, SWS1, SWS2, EN/PWM . . . . . . . . . . . . . . . . . . . . . . . . . . .18V VBAT, FAULT, FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V |VHI - SWS1, SWS2| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V SWD1, SWD2, OVP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
Thermal Information
Thermal Resistance JA (C/W) / JC (C/W) 20 Ld QFN Package (Notes 1, 2). . . . . 39 2.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +105C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER VIN VIN VBAT VBATFAULT ISEN ISDIS RSWITCH VDC ROUTOL ROUTCL IOUT ILIMBOOST ILIMBUCK OVPH OVPL VGATE VGATE VFB VLEVEL FBUV FAULT
VBAT = VIN = 12V, VDC = 5V, TA = -40C to +105C unless otherwise specified. CONDITIONS IOUT = 350mA, 8 LEDs, BUCK/BOOSTN = GND IOUT = 350mA, 5 LEDs, BUCK/BOOSTN = GND, TMAX disabled Normal operating range If VBAT > VBATFAULT, FAULT pin is switched to ground No switching, EN/PWM = 1 No switching, EN/PWM = 0 ISWITCH = 600mA 4.75 VIN < VDC VIN > 6V, F < 100Hz 4 LED output string. VIN = VBAT = 10V BUCK/BOOSTN = GND BUCK/BOOSTN = VDC Upper threshold to enter overvoltage fault mode, TA = +25C Lower threshold to exit overvoltage fault mode, TA = +25C VIN - VFAULT VFAULT - VIN System in regulation, VLEVEL = 1V, VIN = 12V, 6 LEDs Mode = 1, analog control of LED current VLEVEL = 1V, EN/PWM = 3V 9.76 8.16 0.18 0.25 100 160 31 1 3.6 2.4 32 20 12.2 10.2 0.2 23 14.64 12.24 0.22 3 200 MIN 5 2.7 2.7 17.6 21 2.7 0.6 0.15 5 TYP MAX 16 12 16 24 3.5 2.5 0.25 5.25 40 6.5 UNIT V V V V mA A V A A A V V V V V V mV
DESCRIPTION Input Supply Voltage Input Supply Voltage Input Supply Monitor Supply Fault Threshold Supply Current in VIN Supply Current in VIN Power FET On-Resistance Regulated Auxiliary Supply Auxiliary Supply Open Loop Output Resistance Auxiliary Supply Closed Loop Output Resistance Output Drive Current Power Switch Current Limit Power Switch Current Limit Overvoltage Positive Going Voltage Mode Threshold Overvoltage Negative Going Voltage Mode Threshold Protection FET VGS (Gate Clamp) Protection FET VGS (Gate Clamp) Feedback Voltage Light Control Voltage Linear Input Range Feedback Undervoltage Fault
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ISL78100
Electrical Specifications
PARAMETER FBOV FAULT fSW fDIMMING tSWITCH RLSDRIVERL RLSDRIVERH tFAULT tDELAY VFAULTPUMP VBOOST VBUCK VMODEL VMODEH enFAULT disFAULT enTEMP disTEMP TCOMPP TCOMPN TTRIP THYS VEN/PWML VEN/PWMH VDCUVLO RSchottky
.
VBAT = VIN = 12V, VDC = 5V, TA = -40C to +105C unless otherwise specified. (Continued) CONDITIONS VLEVEL = 1V, EN/PWM = 3V MIN 220 800 Mode = 1, modulation signal applied to EN/PWM CGATE = 2nF EN/PWM = 0 EN/PWM = 3V 40 Timed LX switching delay VBAT = VIN = 3V BUCK/BOOSTN = GND BUCK/BOOSTN = VDC MODE = GND MODE = VDC 2/3VDC 0.9VDC 0.96VDC 0.5 0.08 VTEMP/VDC = 0.80 VTEMP/VDC = 0.20 1.26 0.74 135 25 1.2 2.5 2.6 15 23 C C V V V 0.94VDC 1/3VDC 0.85 6 0.4VDC TYP 250 1000 10 100 30 30 50 1 50 52 60 1.24 MAX 300 1150 UNIT mV kHz kHz ns ms ms V V V V V V V V V
DESCRIPTION Feedback Overvoltage Fault Switching Frequency Maximum Recommended PWM Dimming Frequency Load Switch Transition Time Load Switch Driver Impedance Low Load Switch Driver Impedance High Fault Timer Period Start-up Delay Fault Pin Charge Pump Boost Mode Threshold Buck Mode Threshold Mode Low Threshold Mode High Threshold Input Level Applied to TMAX Pin to Enable Fault Protection Input Level Applied to TMAX Pin to Disable Fault Protection Input Level Applied to TEMP Pin to Enable Temperature Compensation Input Level Applied to TEMP Pin to Disable Temperature Compensation VFB Positive Temperature Compensation; VFB/VFBnom VFB Negative Temperature Compensation; VFB/VFBnom Internal Temperature Protection Threshold Internal Temperature Protection Hysteresis EN/PWM Pin Input Low Threshold EN/PWM Pin Input High Threshold VDC Undervoltage Lockout Internal Schottky Diode for Buck
TABLE 1. LIGHT OUTPUT CONTROL, VDC = 5.0V MODE 1 Don't Care 0 TEMP OPERATING MODE
(VDC - 0.25) > V > 0.25V Standard Mode light level to PWM modulation of EN/PWM input; LED bias current determined by LEVEL voltage, nominal 1V V < 0.25V V < (VDC - 0.25) Disable temperature compensation Fixed Bias Mode VFB level internally set to 0.4V, independent of VLEVEL
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ISL78100 Typical Performance Curves
100 8 LEDs 95 ILEDpeak = 380mA 90 EFFICIENCY (%) 85 10%@10kHz 80 75 99%@1kHz 70 65 60 6 8 10 12 VIN (V) 14 16 18 50%@100Hz 10%@1kHz 10%@100Hz 50%@1kHz 100 99%@100Hz 99%@10kHz EFFICIENCY (%) 95 90 85 80 75 99% @ 100Hz 70 65 60 4 6 8 10% @ 100Hz 10 VIN (V) 12 14 16 10% @ 10kHz 5 LEDs ILEDpeak = 380mA 99% @ 10kHz
50%@10kHz
FIGURE 1. 8 LEDs EFFICIENCY vs INPUT VOLTAGE vs DIMMING FREQUENCY AND DUTY CYCLE
FIGURE 2. 5 LEDs EFFICIENCY vs INPUT VOLTAGE vs DIMMING FREQUENCY AND DUTY CYCLE
100
100 95 99%@100Hz EFFICIENCY (%) 99%@10kHz 90 85 80 75 70 65 10 60 0 5 LEDs 8 LEDs
3 LEDs 95 ILEDpeak = 380mA 90
EFFICIENCY (%)
85 80 75 10%@10kHz 70 65 60 4 6 VIN (V) 10%@100Hz 8
ILEDpeak = 380mA PWM = 10kHz 8 LEDs, VIN = 12V 5 LEDs, VIN = 9V 20 40 60 80 PWM DIMMING DUTY CYCLE (%) 100
FIGURE 3. 3 LEDs EFFICIENCY vs INPUT VOLTAGE vs DIMMING FREQUENCY AND DUTY CYCLE
FIGURE 4. 8 AND 5 LEDs EFFICIENCY vs PWM DUTY CYCLE
400 ILEDpeak = 380mA 350 8 LEDs, VIN = 12V 5 LEDs, VIN = 9V 300 3 LEDs, VIN = 5V ILED (mA) 250 200 150 100 50 5 LEDs @ 10kHz 0 0 20 40 60 80 100 PWM DIMMING DUTY CYCLE (%) 8 LEDs @ 1kHz 5 LEDs @ 100Hz 3 LEDs @ 100Hz DILED (%)
4 3 2 1 0 -1 -2 -3 -4 -5 -6 6 8 99% @ 10kHz 99% @ 100Hz 10 12 VIN (V) 14 16 18 10% @ 10kHz 10% @ 100Hz 8 LEDs ILEDpeak = 380mA
8 LEDs @ 10kHz
FIGURE 5. LEDs PWM DIMMING LINEARITY
FIGURE 6. 8 LEDs CURRENT ACCURACY vs INPUT VOLTAGE
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ISL78100 Typical Performance Curves (Continued)
10 8 6 4 DILED (%) DILED (%) 2 0 -2 -4 -6 -8 -10 4 99% @ 100Hz 6 8 10 VIN (V) 12 14 16 10% @ 10kHz 10% @ 100Hz 99% @ 10kHz 5 LEDs ILEDpeak = 380mA 16 14 12 10 8 6 4 2 0 -2 -4 4 5 6 7 VIN (V) 8 9 10 99% @ 100Hz 99% @ 10kHz 3 LEDs ILEDpeak = 380mA
FIGURE 7. 5 LEDs CURRENT ACCURACY vs INPUT VOLTAGE
FIGURE 8. 3 LEDs CURRENT ACCURACY vs INPUT VOLTAGE
400 8 LEDs 395 I LEDpeak = 380mA 390 DUTY CYCLE = 99% 385 ILED (mA) 380 375 370 365 360 355 350 6 8 PWM @ 10kHz PWM @ 100Hz 10 12 VIN (V) 14 16 18 PWM @ 1kHz ILED (mA)
420 415 410 405 400 395 390 385 380 375 370 365 360 355 350
5 LEDs ILEDpeak = 380mA DUTY CYCLE = 99%
99% @ 10kHz
99% @ 100Hz 4 6 8 10 VIN (V) 12 14 16
FIGURE 9. 8 LEDs LINE REGULATION OF PWM DUTY CYCLE OF 99%
FIGURE 10. 5 LEDs LINE REGULATION OF PWM DUTY CYCLE OF 99%
410 405 400 395 390 385 PWM @ 100Hz 380 375 370 365 360 4 5 PWM @ 10kHz ILED (mA) ILED (mA) 3 LEDs ILEDpeak = 380mA DUTY CYCLE = 99%
40 8 LEDs 39 I LEDpeak = 380mA 38 DUTY CYCLE = 10% 37 36 35 34 33 32 31 8 9 10 30 6 8 10 12 VIN (V) 14 16 18 PWM @ 1kHz PWM @ 10kHz PWM @ 100Hz
6
7 VIN (V)
FIGURE 11. 3 LEDs LINE REGULATION OF PWM DUTY CYCLE OF 99%
FIGURE 12. 8 LEDs LINE REGULATION OF PWM DUTY CYCLE OF 10%
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ISL78100 Typical Performance Curves (Continued)
41 5 LEDs 40 ILEDpeak = 380mA DUTY CYCLE = 10% 39 10% @ 100Hz ILED (mA) 38 37 36 35 34 6 8 10 12 VIN (V) 14 16 18 10% @ 10kHz ILED (mA) 42 3 LEDs 41 I LEDpeak = 380mA 40 DUTY CYCLE = 10% 39 38 37 36 35 34 33 32 4 5 6 7 VIN (V) 8 9 10 PWM @ 10kHz PWM @ 100Hz
FIGURE 13. 5 LEDs LINE REGULATION OF PWM DUTY CYCLE OF 10%
FIGURE 14. 3 LEDs LINE REGULATION OF PWM DUTY CYCLE OF 10%
400 RSET = 0.5 350 DUTY CYCLE = 100% 300 ILED (mA) 250 200 150 100 50 3 LED 0 0 0.2 0.4 0.6 VLEVEL (V) 0.8 1.0 5 LED 8 LED IQ (mA)
0.1000
EN/PWM = 0 VLEVEL = 1V TA = +25C
0.0100
0.0010
0.0001 6
8
10
12 VIN (V)
14
16
18
FIGURE 15. LED CURRENT vs VLEVEL BIAS
FIGURE 16. QUIESCENT CURRENT (NON-SWITCHING)
8 LEDs ILED = 350mA
VIN
8 LEDs ILED = 350mA
VIN
LX
LX
IL
IL
FB
FB
FIGURE 17. START-UP WAVEFORMS
FIGURE 18. START-UP WAVEFORMS ZOOM-IN
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ISL78100 Typical Performance Curves (Continued)
LX 8 LEDs VIN = 16V PWM = 100Hz IL LX
8 LEDs VIN = 16V PWM = 10kHz
IL
VOUT (AC COUPLED) FB
VOUT (AC COUPLED) FB
FIGURE 19. 50% PWM DIMMING AT 100Hz
FIGURE 20. 50% PWM DIMMING AT 10kHz
LX
LX
8 LEDs VIN = 12V PWM = 1kHz IL IL
VOUT (AC COUPLED) FB 8 LEDs VIN = 16V
VOUT (AC COUPLED) DUTY CYCLE = 50% PWM = 1kHz FB
FIGURE 21. 10% PWM DIMMING AT 1kHz
FIGURE 22. 50% PWM DIMMING AT 1kHz ZOOM-IN
LX
LX
TRANSIENT RESPONSE WHEN LOAD DYNAMICALLY CHANGES FROM 8 LEDs TO 7 LEDs VIN = 12V 8 LEDs VO ILED = 350mA VOUT (WITH 25.6V OFFSET) 7 LEDs VO
TRANSIENT RESPONSE WHEN LOAD DYNAMICALLY CHANGES FROM 7LEDs TO 8LEDs VIN = 12V 8 LEDs VO ILED = 350mA VOUT (WITH 25.6V OFFSET) 7 LEDs VO
FIGURE 23. TRANSIENT RESPONSE OPERATES FROM 8 TO 7 LEDs
FIGURE 24. TRANSIENT RESPONSE OPERATES FROM 7 TO 8 LEDs
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ISL78100 Typical Performance Curves (Continued)
FB = 0V VOUT VOUT VIN IL
ILED
8LEDs VIN = 3.3V ILED = 380mA
FIGURE 25. OVP AND RESET
FIGURE 26. CURRENT LIMIT
Typical Boost Mode Application Diagram
VBAT
VIN FAULT VBAT VDC 0.1F TEMP SENSOR VDC BUCK/BOOSTN TEMP TMAX PWM EN/PWM MODE LEVEL 1V
VHI SWD1 SWD2 OVP
SWS1 SWS2 ENL FB GND
FIGURE 27. TYPICAL BOOST MODE APPLICATION CIRCUIT
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ISL78100 Pin Descriptions
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME VDC VHI OVP SWD1 SWD2 DESCRIPTION Internally regulated 5V supply, tracks VIN for input voltages less than 5V. LDO output can also be biased with external supply if VIN is <5.5V. A minimum of 3.3F decoupling capacitor is needed in this pin. Power FET gate drive supply. Can be biased with external supply if VIN is <5.5V Overvoltage monitor input; tie to VOUT for normal operation NMOS power FET drain NMOS power FET drain
BUCK/BOOSTN Tie to GND for BOOST operation and to VDC for Buck operation LEVEL TEMP FB TMAX SWS2 SWS1 EN/PWM MODE ENL VBAT NC GND FAULT VIN Sets LED bias current level; VFB(nominal) = VLEVEL/5 Temperature reference, tie to GND to disable temperature compensation LED current feedback Maximum LED temperature set point; if TEMP voltage exceeds TMAX, FB set point will be reduced NMOS power FET source NMOS power FET source Chip enable and light modulation PWM dimming input Digital Input; tie to GND to set FB reference to 400mV, tie to VDC to control FB reference with LEVEL input LED load isolation MOS gate driver Input supply monitor Leave floating (internally connected) Ground return and FB ground reference Gate drive of fault protection FET. Driven low under fault conditions Input supply
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Functional Block Diagram
2.7V TO 16V L VBAT GND CLOCK AND RAMP GENERATOR START-UP CHARGE PUMP VSTART FAULT CONTROL AND TIMER VSTART HALT LDO AND REF REF CLK RAMP FAULT VIN VDC VHI
10
BUCK/ BOOSTN
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OVP
SWD2 VDC REF POR LEVEL (T) EN O/P LEVEL LIGHT CONTROL VDC EN O/P MODE EN/PWM MODE CONTROL TEMPERATURE COMPENSATION LOAD CURRENT SENSE FB ENL CLK RAMP HALT INNER LOOP PWM CONTROL AND CURRENT LIMIT SWD1
ISL78100
SWS1
FET CURRENT SENSE
SWS2
ISL78100
HALT TEMP TMAX
FIGURE 28. ISL78100 BLOCK DIAGRAM
ISL78100 Theory of Operation
General Description
The ISL78100 is a flexible, highly integrated high-power LED driver consisting of a PWM switching controller and integrated 36V NDMOS power FET. The device can drive up to 8 series high-power LED's at currents up to 1A at 16V input or 5 LEDs at current up to 350mA at 2.7V input. The control loop can be configured as either a boost or buck regulator with the configuration of the BUCK/BOOSTN pin, providing an output voltage above or below the input supply voltage, depending on the number of stacked LEDs. The controller operates from 2.7V to 16V depending on the numbers of LEDs and current required and can be powered by a single lithium ion battery, 5V or 12V regulated supplies or automotive electrical systems. LED current is sensed through a low value resistor in series with the LED. A thermistor can be used to implement a thermal protection scheme to limit the maximum LED temperature to a preset desirable level.
VOLTAGE FEEDBACK LEVEL SHIFT GND + ISL78100 VDC/2 VIN FB
RSENSE 0.5
FIGURE 29. FB REFERENCE AUTO SWITCH
Start-up
To maximize external PWM switching speed, the ISL78100 does not include an internal soft-start circuit. When VDC exceeds the power-on reset threshold, switching is delayed for 1ms (tDELAY) allowing the output capacitor to charge through the inductor. If soft-start control is required, a suitable application circuit is shown in Figure 30.
VBAT VBAT FAULT ISL78100 VIN SWD1 SWD2 C1 4.7nF R1 FB SWS1 SWS2 R2 2k 100 0.5 RSENSE 10H L1 VOUT COUT 20F
Switching Regulator
The ISL78100 employs a current mode PWM control scheme with a nominal switching frequency of 1MHz. This provides fast transient response and enables the use of low profile inductors and compact multilayer ceramic capacitors. Settling time is optimized by the use of a simple control loop without an error amplifier, relying instead on intrinsic gain within the direct summing path. Due to the lower loop gain, offset must be accounted for when setting up initial LED bias current. Refer to the "Application Configurations" on page 11 of the datasheet for further information. Figure 28 shows a block diagram of the system.
FIGURE 30. EXTERNAL SOFT-START CIRCUIT
Application Configurations
Operating Modes
The ISL78100 can operate as either a buck or boost regulator. Hardwire BUCK/BOOSTN to GND for boost mode or to VDC for buck mode. In buck mode the power NDMOS drive circuit is "floated" (boot-strapped) allowing the NDMOS gate to be driven above VIN to fully enhance the power NDMOS. An internal Schottky diode between VDC (5V) and VHI reduces external component count. Use a ceramic capacitor of at least 50nF between VHI and SWS1/2 to bootstrap VHI.
Light Level Control
Two light control schemes are provided: 1. An external PWM signal via the EN/PWM pin, providing low frequency PWM dimming. 2. Bias current level adjustment via the LEVEL input or fixed internal bias.
PWM Dimming
LED color temperature varies with bias current. In backlighting applications, PWM dimming offers better control of color temperature because current through the LEDs is kept constant. A 5V gate driver (ENL) synchronized to EN/PWM can be used to control an external N-Channel FET and disconnect the LED stack during the PWM off-period. The switch prevents discharge of the output capacitor by the LED load, maintaining a constant bias independent of PWM duty cycle. Operation at 1kHz PWM rate is shown in Figure 31 and Figure 32. The load disconnect switch improves PWM dynamic range, linearity and color temperature control. To further improve the linearity of PWM dimming, an internal timer delays system shutdown via EN/PWM for 50ms.
LED Load Connection
ISL78100 includes an auto-sensing FB level shift circuit that enables the LED load to be connected to either GND or VIN. An internal sense circuit monitors the FB pin voltage. When the level exceeds VDC/2, the feedback reference voltage is switched from GND to VIN. Refer to the application section of the datasheet for typical application schematics.
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ISL78100
.
The value of VFB should be limited to between 50mV and 450mV for linear operation. For minimum light output, VFB may be set below 50mV. With MODE tied to GND, voltage across the feedback resistor is set at ~400mV via an internal reference. In either operating mode, if LED temperature control is enabled, the value of VFB will be reduced when maximum LED temperature is exceeded.
Input Overvoltage
For automotive applications, an external high voltage NFET driven by the FAULT pin disconnects the device from the input supply in response to voltage spikes on the input supply. During start-up, an internal charge pump drives the FAULT pin above the input voltage, ensuring the NFET is fully enhanced and powering up the device. In normal operation, the switching node of the boost regulator or the floating supply of the buck regulator is used to pump FAULT above VIN. On detection of an overvoltage, the FAULT pin is discharged to GND. The gate to source voltage of the NDMOS is internally limited to 15V to prevent voltage stress.
FIGURE 31. OPERATION WITH ENL CONTROLLED FET
Fault Protection
The external NFET is also used as a fault protection switch, disconnecting the input supply if a fault occurs for more than 50ms. The system monitors feedback voltage regulation, output overvoltage and input overvoltage. For applications not requiring input voltage or fault protection, connect VBAT and VIN directly together. All faults except input supply overvoltage latch the ISL78100 into an off-state that can be cleared by either power cycling the input supply or the EN/PWM pin. Connecting the TMAX pin to VDC disables the fault latch function (LED over-temperature control is also disabled).
FIGURE 32. OPERATION WITH NO ENL CONTROLLED FET
Output Overvoltage Protection (OVP)
If the FB pin is shorted to ground or an LED fails open circuit, output voltage in BOOST mode can increase to potentially damaging voltages. An optional overvoltage protection circuit can be enabled by connection of the OVP pin to the output voltage. The device will stop switching if the output voltage exceeds OVPH and re-start when the output voltage falls below OVPL. During sustained OVP fault conditions, VOUT will saw-tooth between the upper and lower threshold voltages at a frequency determined by the magnitude of current available to discharge the output capacitor and the value of output capacitor used. The OVP threshold can be set to a lower value by using an external zener diode and resistor, as shown in Figure 33. R1 should be adjusted to minimize offset in the FB voltage due to FB pin input current. A value of 100 is recommended.
Bias Current Dimming
Current in the LED load is determined by the value of the feedback resistor and the target feedback regulation voltage as shown in Equation 1:
V FB I LED = ----------------------R SENSE (EQ. 1)
With MODE tied to VDC, voltage across the feedback resistor is set by VLEVEL as shown in Equation 2:
V LEVEL V FB = --------------------5 (EQ. 2)
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ISL78100 Component Selection
VBAT VBAT FAULT VIN ISL78100 SWD1 SWD2 ZOVP FB SWS1 SWS2 R1 100 0.5 RSENSE 10H L1 VOUT COUT 20F
Input Capacitor
Switching regulators require input capacitors to deliver peak charging current and to reduce the impedance of the input supply. This reduces interaction between the regulator and input supply, improving system stability. The high switching frequency of the loop causes almost all ripple current to flow in the input capacitor, which must be rated accordingly. Considerably more input current ripple is generated in buck mode than boost mode. In buck mode input current is alternately switched between IOUT and zero. The RMS current flow in the input capacitor is given by Equation 3:
I CAPRMS = I OUT * ( D - D )
2
FIGURE 33. EXTERNAL OVP CIRCUIT
Over-Temperature Shutdown
An internal sense circuit disables PWM switching if the die temperature exceeds +135C. Switching is re-enabled when the temperature falls below +100C.
(EQ. 3)
Where: D = Duty Cycle The input current is maximum for D = 0.5 and when IOUT approaches current limit (2.4A) giving a value of around 1.2A. A capacitor with low internal series resistance should be chosen to minimize heating effects and improve system efficiency, such as X5R or X7R ceramic capacitors, which offer small size and a lower value of temperature and voltage coefficient compared to other ceramic capacitors. In boost mode input current flows continuously into the inductor, with an AC ripple component proportional to the rate of inductor charging only and smaller value input capacitors may be used. It is recommended that an input capacitor of at least 10F be used. Ensure the voltage rating of the input capacitor is suitable to handle the full supply range. In automotive applications, the input capacitor can be protected from exposure to high voltages present during fault conditions (load dump) by connecting it downstream of the fault protection switch, as shown in Figures 39 and 40.
Internal 5V LDO
An internal LDO between VIN and VDC regulates VDC to 5V, to power control and gate drive circuits when VIN exceeds 5.1V. In normal operation decouple VDC with at least 3.3F. In applications where the input supply is less than 5.5V, VDC should be tied directly to VIN.
LED Temperature Control
LED lifetime reduces dramatically with elevated temperature. An over-temperature control circuit utilizing the thermistor voltage at TEMP reduces the LED bias current when VTEMP exceeds the threshold voltage on TMAX. To minimize noise injection, use a potential divider between VDC and GND to set the voltage on TMAX, as shown in Figure 34. The value of TMAX for a specific threshold temperature is determined by the choice of thermistor temperature coefficient. Disable the function by connecting the TMAX pin to VDC and TEMP pin to GND.
THERMISTOR
CREG 0.47F VIN VDC LDO TMAX
CLOSE TO LEDs RM1 20k RM2 80k
Inductor
Careful selection of inductor value will optimize circuit operation. Inductor type and value influence many key parameters, including ripple current, current limit, efficiency, transient performance and stability. Internal slope compensation has been optimized for inductor values between 4.7H and 10H. Ensure the inductor current rating is capable of handling the current limit value in the configuration used (2.4A for buck, 3.5A for boost). If an inductor core is chosen with too low a current rating, saturation in the core will cause the effective inductor value to fall, leading to an increase in peak to average current level, poor efficiency and overheating in the core.
RSENSE 0.5
+ FB LEVEL CURRENT TEMPERATURE COMPENSATION ISL78100 TEMP RT GND 10k
FIGURE 34. OVER-TEMPERATURE CIRCUIT
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Rectifier Diode
A high speed rectifier diode is necessary to prevent excessive voltage overshoot, especially in the boost configuration. Low forward voltage and reverse leakage current will minimize losses, making Schottky diodes the preferred choice. Similarly to the inductor, a diode with a suitable current rating to handle current limit in the configuration must be used. In buck mode:
( V IN - V OUT ) x D D V RIPPLE = ---------------------------------------------- x -------------------------- + ESR f x C 2 x fs x L s OUT (EQ. 7)
where:
V OUT D = --------------V IN (EQ. 8)
Output Capacitor
The output capacitor acts to smooth the output voltage and in the boost configuration supplies load current directly during the conduction phase of the power switch. Ripple voltage consists of two components, the first due to charging and discharging of the capacitor; the second due to IR drop across the ESR of the capacitor by inductor ripple current. In boost mode:
IO - DV RIPPLE = --------------- x ------ + I LPK x ESR C OUT F S (EQ. 4)
For a low ESR ceramic capacitor, output ripple is dominated by the charging and discharging of the output capacitor. Care should be taken to ensure the voltage rating of the capacitor exceeds the maximum output voltage.
Compensation
The ISL78100 employs a direct summing control loop with current feedback. No error amplifier is used in the system. The arrangement provides fast transient response and makes use of the output capacitor to compensate the loop. The effect of the pole associated with the inductor is minimized by the current feedback. The number of LEDs, their DC bias current and the value of feedback resistor alter loop stability due to their effect on feedback factor, which is heavily influenced by the small signal impedance of the LEDs. Generally, higher numbers of LEDs, lower bias levels and smaller values of feedback resistor will require smaller output capacitors to achieve loop stability. A combination of low ESR electrolytic and ceramic capacitors may be used to reduce implementation costs.
where:
V OUT - V IN D = ------------------------------V OUT (EQ. 5)
and
IO ( V OUT - V IN ) ( 1 - D ) I LPK = ------------ + ------------------------------------ x ----------------2xL 1-D fs (EQ. 6)
TABLE 2. BOOST MODE COMPENSATION. 2.7V OPERATION VOUT (V) VFB 50mV IOUT 50mA LED's Electrolytic Ceramic 100mV 100mA Electrolytic Ceramic 200mV 350mA Electrolytic Ceramic 200mV 1A Electrolytic Ceramic TABLE 3. BOOST MODE COMPENSATION 6V OPERATION VOUT (V) VFB 50mV IOUT 50mA LED's Electrolytic Ceramic 100mV 100mA Electrolytic Ceramic 200mV 350mA Electrolytic Ceramic 200mV 1A Electrolytic Ceramic 7 2 94F 40F 141F 60F 141F 60F 94F 40F 10.5 3 47F 20F 47F 60F 47F 60F 47F 40F 60F 47F 40F ILIM 60F ILIM 40F ILIM 40F ILIM 40F ILIM 40F 40F 40F 40F 40F 20F 20F 20F 20F 14 4 17.5 5 21 6 24.5 7 28 8 7 2 94F 40F 94F 60F 94F 60F ILIM 60F 47F 40F ILIM 40F 47F 40F ILIM 40F 47F 40F ILIM ILIM ILIM ILIM 40F ILIM ILIM ILIM 10.5 3 47F 20F 40F 20F 20F 14 4 17.5 5 21 6 24.5 7 DMAX 28 8 DMAX
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TABLE 4. BOOST MODE COMPENSATION 12V OPERATION VOUT (V) VFB 50mV IOUT 50mA LED's Electrolytic Ceramic 100mV 100mA Electrolytic Ceramic 200mV 350mA Electrolytic Ceramic 200mV 1A Electrolytic Ceramic DMIN DMIN DMIN DMIN DMIN DMIN DMIN DMIN DMIN DMIN DMIN DMIN 60F 47F 40F 47F 40F 47F 20F 40F 47F 20F 47F 20F 47F 20F 40F 40F 40F 40F 40F 40F 40F 40F 7 2 10.5 3 14 4 17.5 5 21 6 24.5 7 28 8
CERAMIC CAPACITORS Many ceramic capacitors have strong voltage and temperature coefficients, which reduces effective capacitance as the applied voltage or operating temperature is increased. Pay careful attention when selecting ceramic capacitor type. X5R and X7R families provide much better stability than Y5V, which should generally be avoided unless additional capacitance is added to compensate for the significant changes in value, which occurs overvoltage and temperature.
TABLE 5. CERAMIC CAPACITOR VARIABILITY CAPACITOR TYPE X7R, 10V X5R, 25V Y5V, 6.3V TYPICAL VOLTAGE VARIATION -30% at 10V -50% at 25V -90% at 6.3V TEMPERATURE VARIATION -15% at +125C -9% at +85C -65% at +85C
* Place several via holes (thermal vias) under the chip to a backside ground plane to improve heat dissipation * Maximize the copper area around the thermal vias to spread heat away from the chip.
Cost-Sensitive Applications
For cost-sensitive applications, the BOM can be reduced considerably by: 1. Removing temperature compensation 2. Removing the fault-protection switch 3. Removing the load isolation switch 4. Switching the FB into internal fixed bias mode (400mV across VFB) In this configuration, light level may be controlled using the EN/PWM input to modulate the output current. In the absence of the load isolation switch, LED bias current will vary with PWM duty cycle, due to the discharge of the output capacitor by the LED's during the PWM off-time. Therefore, low dimming frequencies can only be used in such an application.
Layout Considerations
PCB layout is very important for the converter to function properly. The following general guidelines should be followed: * Separate the Power Ground and Signal Ground; connect them only at one point close to the GND pin. * Maximize the Power Ground area as much as possible. It is essential to ensure the Power Ground return between CIN, COUT, and SWS1,2 as least obstructive as possible. * Place the input capacitor close to VIN and SWS1, SWS2 pins in boost mode. * Make the following PC traces as short as possible: - from SWD1, SWD2 to the inductor in boost mode - from SWS1,SWS2 to the inductor in buck mode - from COUT to PGND * Feedback signals levels are small to improve efficiency. Ensure the reference connection (GND or VIN) between the sense resistor and IC pin doesn't carry switching current.
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ISL78100 Boost Mode Application Diagram
VBAT
VIN FAULT VBAT VDC TEMP TMAX EN EN/PWM MODE LEVEL
VHI SWD1 SWD2 OVP SWS1 SWS2 ENL FB GND
BUCK/BOOSTN
FIGURE 35. BASIC BOOST APPLICATION CIRCUIT
Boost Mode with Overcurrent Fault and LED Temperature Protections Application Diagram
VBAT
VIN FAULT VBAT VDC TEMP SENSOR TEMP TMAX EN EN/PWM MODE VLEVEL (0V TO 2.5V) LEVEL
VHI SWD1 SWD2 OVP SWS1 SWS2 ENL FB GND
BUCK/BOOSTN
FIGURE 36. BOOST MODE APPLICATION WITH OVERCURRENT FAULT PROTECTION AND LED TEMPERATURE PROTECTION
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ISL78100 Typical Buck Application Diagram
VBAT VIN FAULT VBAT VDC TEMP TMAX EN EN/PWM MODE LEVEL VHI SWD1 SWD2 OVP SWS1 SWS2 ENL FB GND
BUCK/BOOSTN
FIGURE 37. BASIC BUCK APPLICATION CIRCUIT
Buck Mode with Overcurrent Fault and LED Temperature Protections Application Diagram
VBAT
VIN FAULT VBAT VDC TEMP SENSOR TEMP TMAX EN EN/PWM MODE VLEVEL (0V TO 2.5V) LEVEL
VHI SWD1 SWD2 OVP SWS1 SWS2 ENL FB GND
BUCK/BOOSTN
FIGURE 38. BUCK MODE WITH OVERCURRENT FAULT AND LED TEMPERATURE PROTECTIONS APPLICATION
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 17
FN6626.0 December 17, 2007
ISL78100 Automotive Applications
The LED load and ISL78100 may be protected against load dumps and other electrical faults in automotive supplies with a minor addition to the standard application schematic: * A reverse transient automotive-rated protection power Schottky must be added in series with the input supply * A 500 current limit resistor must be inserted in series with the VBAT pin * The fault protection NFET must be specified to handle 100V VDS conditions. The protection circuit is applicable to buck, boost, and supply-return load applications. A small reduction in efficiency is caused by the drop in the power Schottky. Unless alternative transient protection is provided, minimum BOM automotive applications must include the circuit changes noted previously.
Automotive Boost Application Diagram
VBAT RLIM 500
VIN FAULT VBAT VDC TEMP SENSOR TEMP TMAX EN EN/PWM MODE VLEVEL (0V TO 2.5V) LEVEL
VHI SWD1 SWD2 OVP SWS1 SWS2 ENL FB GND
BUCK/BOOSTN
FIGURE 39. AUTOMOTIVE BOOST MODE APPLICATION DIAGRAM
Automotive Minimum BOM Boost Application Diagram
VBAT
VIN FAULT VBAT VDC TEMP TMAX EN EN/PWM MODE VLEVEL (0V TO 2.5V) LEVEL
VHI SWD1 SWD2 OVP SWS1 SWS2 ENL FB GND
BUCK/BOOSTN
FIGURE 40. AUTOMOTIVE MINIMUM BOM BOOST MODE APPLICATION
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Package Outline Drawing
L20.4x4C
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 11/06
4X 4.00 A B 6 PIN 1 INDEX AREA 15 1 16 2.0 6 PIN #1 INDEX AREA
16X 0.50 20
4.00
2 .70 0 . 15
11
5
(4X)
0.15 10 6 0.10 M C A B 4 20X 0.25 +0.05 / -0.07
TOP VIEW
20X 0.4 0.10
BOTTOM VIEW
SEE DETAIL "X" 0.10 C C BASE PLANE ( 3. 8 TYP ) ( 2. 70 ) ( 20X 0 . 5 ) SEATING PLANE 0.08 C
0 . 90 0 . 1
SIDE VIEW
( 20X 0 . 25 ) C ( 20X 0 . 6) 0 . 00 MIN. 0 . 05 MAX. 0 . 2 REF 5
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
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